Tablets

Driving Exceptional User Experiences In Next Generation Tablets

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Tablet architecture continues to evolve, adding more sensors, improving quality of existing sensors and displays which drive better user experience with crisp imagery and perfect details. In addition, device manufacturers are racing toward lower power consumption and slim size devices. Lattice FPGAs provide the bridging and distributed processing capabilities to elevate some of the challenges designer are facing on the road to innovative form factors with ultra slim designs.

Lattice’s solutions running on optimized low power FPGAs provide:

  • Flexible and low latency sensor data aggregation, bridging, data buffering and processing from a wide variety of sensors
  • MIPI CSI and DSI image sensor and display bridging
  • New form factors by improving board to board connectivity

Jump to

Block Diagram

Tablets

Example Use Cases

Sensor Fusion and I/O Expansion

  • Interface to a wide variety of sensors to create rich user experience
  • Flexible preprocessing including arbitration, time stamping, and filtering
  • Create programmable sensor fusion algorithms

Image Sensor Bridging

  • Connect wide a variety of image sensors to processors
  • MIPI PHY supports up to 2.5 Gbps/lane, up to four lanes
  • Flexible host interfacing including CSI, SPI, and PCIe
  • Flexible processing for video data muxing and Stitching

Display Bridging

  • Bridge between displays and processors when display interface is not supported native by the processor
  • Use the FPGA internal memory resources for compression and buffering
  • Expand the number of processor display interfaces

Reference Designs

Key Phrase Detection

Reference Design

Key Phrase Detection

Continuous searches for a key phrase utterance via a digital MEMS microphone. Can be re-configured to work with any trained word or phrase.
Key Phrase Detection
Human Face Identification AI

Reference Design

Human Face Identification AI

Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.
Human Face Identification AI
Human Presence Detection

Reference Design

Human Presence Detection

Uses Lattice sensAI IP to continuously search for the presence of a human and reports results. Can be adapted to detect any other object.
Human Presence Detection
Object Counting AI

Reference Design

Object Counting AI

An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
Object Counting AI

Demos

Key Phrase Detection

Demo

Key Phrase Detection

Uses artificial intelligence (AI) to detect a specific key-phrase using a tiny, low-power iCE40 UltraPlus FPGA
Key Phrase Detection
Human Counting AI Demo

Demo

Human Counting AI Demo

Human upper-body detection and counting demonstration utilizes Lattice’s ECP5 FPGA and a Convolutional Neural Network (CNN) acceleration engine
Human Counting AI Demo
Human Face Detection AI Demo

Demo

Human Face Detection AI Demo

Uses Lattice sensAI IP to detect human faces on a tiny, low-power iCE40 UltraPlus FPGA implementing AI at the edge. Adaptable to detect other objects.
Human Face Detection AI Demo
Human Face Identification AI

Demo

Human Face Identification AI

Register and identify faces without retraining, eliminating the need for uploading images and lengthy retraining using a GPU.
Human Face Identification AI

IP Cores

CNN Plus Accelerator IP

IP Core

CNN Plus Accelerator IP

Implement Ultra-Low Power AI solutions with CNNs. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
CNN Plus Accelerator IP
Convolutional Neural Network (CNN) Accelerator IP

IP Core

Convolutional Neural Network (CNN) Accelerator IP

Implement AI solutions with CNNs from common or custom networks. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
Convolutional Neural Network (CNN) Accelerator IP
Convolutional Neural Network (CNN) Compact Accelerator

IP Core

Convolutional Neural Network (CNN) Compact Accelerator

Implement AI solutions with CNNs or BNNs that have power consumption in the mW range. Works with Lattice Neural Network Compiler software tool.
Convolutional Neural Network (CNN) Compact Accelerator
CSI-2/DSI D-PHY Receiver

IP Core

Development Kits & Boards

Embedded Vision Development Kit

Board

Embedded Vision Development Kit

Three-board Video Interface Platform (VIP) modular kit. Includes 2 MIPI/D-PHY camera input, FPGA processing, HDMI output. More Input/Output boards available.
Embedded Vision Development Kit
CrossLink-NX Evaluation Board

Board

CrossLink-NX Evaluation Board

For general evaluation and development with CrossLink-NX, includes many flexible interfaces such as FMC and PMOD with generous device IO access
CrossLink-NX Evaluation Board
HM01B0 UPduino Shield

Board

HM01B0 UPduino Shield

A complete development kit for implementing Artificial Intelligence (AI) using vision and sound as sensory inputs to a low-cost, low-power iCE40 UltraPlus FPGA.
HM01B0 UPduino Shield
CrossLinkPlus LIF-MDF6000 Master Link Board

Board

CrossLinkPlus LIF-MDF6000 Master Link Board

This kit with the LIF-MDF6000 Master Link Revision B Board can be used to build bridging solutions between various video formats. You can use this hardware to validate your own designs.
CrossLinkPlus LIF-MDF6000 Master Link Board

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Quality & Reliability

Reference Material to Help Answer Your Questions

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